| Partner | Publication | ||||
| NXP-NL | ELESIS, Poster in Nanolectronic Forum. Munich November 2012. | ||||
| NXP-NL | Reducing Test Cost for Mixed Signal Test from TOETS to ELESIS, European Test Symposium 2012. | ||||
| NXP-NL | European Library-based flow of Embedded Silicon Test Instruments, Nanoelectronic Forum, 2012 | ||||
| TEMENTO SYSTEMS | IP Cores Based Test of Electronic Boards – European Test Symposium 2013 | ||||
| LIRMM / NXP-FR | David-Grignot, S.; Azais, F.; Latorre, L.; Lefevre, F., ” Analog Measurements based on Digital Test Equipment for Low-Cost Testing of Analog/RF Circuits,” in Test Symposium (ETS), 2013 18th IEEE European (Poster), 27-30 May 2013 | ||||
| CEA | Sébastien Sarrazin, Samuel Evain, Lirida Alves de Barros Naviner, Yannick Bonhomme, Valentin Gherman, “Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection, DATE 2013 | ||||
| FEUP | B-Splines Based Built-in Self-Testing of a RF Power Amplifier, DCIS 2012 | ||||
| LIRMM | Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation, IEEE Transactions on Very Large Scale Integraiton (TVLSI), vol.21, no.5, pp. 958-970, 2013 | ||||
| IROC/TIMA | A Standards Based Approach to the Reliability Specification of IP Components, IPSOC 2012 | ||||
| IROC | Subtleties of Single Event Upset Analysis and Mitigation in Sequential Cells, IEEE International Reliability Innovations Conference 2013 | ||||
| IROC | Reliability Analysis and Modelling for Complex Silicon Devices, ETS 2013 | ||||
| NXP-NL | Industrial Application of IEEE P1687 for an Automotive Product – case analysis in cooperation with Mentor Graphics, EUROMICRO Digital System Design Conference 2013 | ||||
| ST | PLL Jitter BIST for SOC’s, Grenoble DTC 2012 | ||||
| TIMA/ST | Reduced code linearity testing of pipeline ADCs. IEEE Design & Test of Computers, 2013 | ||||
| TIMA | Statistical learning for test and control of analog/RF circuits,VARI 2014, September 2013, Karlsruhe, Germany | ||||
| TIMA | True non-intrusive sensors for RF built-in test. IEEE International Test Conference, September 2013, Anaheim, USA | ||||
| TIMA | Fault modeling and diagnosis for nanometric analog circuits. IEEE International Test Conference, September 2013, Anaheim, USA | ||||
| TIMA/ST | Reduced code linearity testing of pipeline ADCs in the presence of noise. IEEE VLSI Test Symposium, Berkeley, CA, USA, April-May 2013 | ||||
| TIMA | Defect-oriented non-intrusive RF test using on-chip temperature sensors. IEEE 31st VLSI Test Symposium, Berkeley, CA, USA, April-May 2013. | ||||
| LIRMM | Ayari, H.; Azais, F.; Bernard, S.; Comte, M., “Implementing model redundancy in predictive alternate test to improve test confidence,” in Test Symposium (ETS), 2013 18th IEEE European , vol., no., pp.1-1, 27-30 May 2013 | ||||
| LIRMM / NXP-FR | Accurate and Efficient Analytical Electrical Model of Antenna for NFC Applications, IEEE 11th NEWCAS conference, Paris, June 16-19, 2013 () | ||||
| LIRMM | Analysis and Path Delay Variations in the Presence of Crosstalk Effects, South European Test Seminar (SETS), Obergurgl, Austria, March 2013. | ||||
| NXP-NL | ELESIS Posters participation at Nanoelectronic Forum, Barcelona, November 2013 | ||||
| FEUP | o Antonio J. Salazar, Bruno Mendes, José M. Da Silva, Miguel V. Correia, “Built-In Self-Testing Infrastructure and Methodology for an EMG Signal Capture Module”. 2nd Int. Conf. on Global Health Challenges, GLOBAL HEALTH 2013 November 17 – 22 – Lisbon | ||||
| FEUP | A Transceiver for E-Textile Body-Area-Networks with Built-in Line Fault Detection, DCIS 2013 NOVEMBER 27-29, 2013, DONOSTIA-SAN SEBASTIAN | ||||
| IROC | Algorithm for Fast Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance, SELSE 2014 | ||||
| UT | A. Rohani and H.G. Kerkhoff, “Microprocessors and microsystems”, 37 (2). pp. 147-154. ISSN 0141-9331. 2013. | ||||
| UT | A. Rohani, H.G. Kerkhoff, E. Costenaro, and D. Alexandrescu, “Pulse-length determination techniques in the rectangular single event transient fault model”, in: IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XIII), IEEE Computer Society, ISBN 978-1-4799-0103-6, Samos, Greece. pp. 2013-2018, 16 Jul 2013. | ||||
| UT | J. Wan and H.G. Kerkhoff, “An Embedded Offset and Gain Instrument for OpAmp IPs”, DATE, Dresden, 2014. | ||||
| TIMA/ST | A. Laraba, H.-G. Stratigopoulos, S. Mir, H. Naudet and G. Bret. Reduced code linearity testing of pipeline ADCs. IEEE Design & Test of Computers , Vol. 30, No. 6, pp. 80-88, November-December 2013. | ||||
| TIMA | S. Mir, “Analog/RF test techniques”, Invited Tutorial, 14th European Test Symposium/Test Spring School, Paderborn, Germany, May 2014. | ||||
| TIMA | M. Dubois, H. Stratigopoulos, M. Barragán, R. Alhakim and S. Mir, “Analog/RF test problem solving with statistically sampled data”, Invited Talk (“Elevator Talk”) at the 32nd IEEE VLSI Test Symposium, Napa, USA, May 14-16, 2014. | ||||
| TMA | A. Laraba. Design-for-test of pipeline analog-to-digital converters. PhD Thesis, University of Grenoble, France, September 2013. | ||||
| IROC | New Approaches for Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance, IOLTS 2014 | ||||
| IROC | Managing SER Costs of Complex Systems through Linear Programming, IOLTS 2014 | ||||
| UT | Jinbo Wan and H. G. Kerkhoff, “An arbitrary stressed NBTI compact model for analog/mixed-signal reliability simulations,” in International Symposium on Quality Electronic Design (ISQED), Santa Clara CA, pp. 31–37, 2013. | ||||
| UT | Muhammad A. Khan, and Hans G. Kerkhoff, “Analysing Degradation Effects in Charge-Redistribution SAR ADCs,” in IEEE Int. Symp. On Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), New York USA, pp. 65-70, 2013. | ||||
| UT | Muhammad A. Khan, and Hans G. Kerkhoff, “Monitoring operating temperature and supply voltage in achieving high system dependability,” 8th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2013, 26-28 Mar 2013, Abu Dhabi, UAE. pp. 108-112 | ||||
| UT | Hans G. Kerkhoff, Jinbo Wan, and Young Zhao, “Linking Aging Measurements of Health-Monitors and Specifications for Multi-Processor SoCs,” in 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Santorini Greece, pp. 52-57, 2014. | ||||
| UT | Alireza Rohani and H. G. Kerkhoff, “Two Soft-Error Mitigation Techniques for Functional units of DSP Processors,” European Test Symposium (ETS), Paderborn, May 2014. | ||||
| UT | Muhammad A. Khan and Hans G. Kerkhoff, “Studying DAC Capacitor-Array Degradation in Charge-Redistribution SAR ADCs ” in Proc. DDECS, Warsaw Poland, pp.15-20, 2014. | ||||
| FEUP | Antonio Salazar: Mixed-signal Test and Measurement Framework for Wearable Monitoring System. Poster at PhD Forum, DATE Conference, 2014. | ||||
| FEUP | Antonio J. Salazar, José M. Da Silva, Miguel V. Correia, Bruno Mendes, “Built-In Self-Testing Infrastructure and Methodology for an EMG Monitoring Sensor Module”, accepted for publication in the International Journal On Advances in Systems and Measurements, v7, no. 1&2, 2014. | ||||
| CEA | T Bonnoit, D Morche, C Dehos, E de Foucauld, “Robust BER Estimator for DBPSK Modulation”, accepted 12th IEEE NEWCAS 2014 | ||||
| NXP-NL | ELESIS towards sophisticated Test Methods, European Test Symposium 2014, Paderborn, Germany | ||||
| NXP-NL | Nanoelectronic Forum: European Library based Flow of Embedded Silicon Test Instruments, Barcelona, Nov 2013 | ||||
| FEUP | Antonio J. Salazar, José M. Da Silva, Miguel V. Correia, “An I2C Based Mixed-Signal Test and Measurement Infrastructure”, to be presented at the 19th IEEE IMS3TW workshop, September 2014 | ||||
| IROC | Olivier Lauzeral, Enrico Costenaro, Rémi Gaillard, John Cawley, Dan Alexandrescu, Adrian EvansL “Supply Chain Management for Reliability: Identifying SER-critical components in a large system-Bill Of Material”, IRIC 2014 | ||||
| LIRMM | H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzerho, and M. Renovell, “Enhancing Confidence in Indirect Analog/RF Testing against the Lack of Correlation between Regular Parameters and Indirect Measurements,” Microelectronics Journal, vol. 45, pp. 336–344, Mar. 2014. | ||||
| LIRMM | H. Ayari, F. Azais, S. Bernard, M. Comte, V. Kerzerho, and M. Renovell, “New implementions of predictive alternate analog/RF test with augmented model redundancy,” in DATE’14 : Design, Automation and Test in Europe Conference and Exhibition, (Dresden, Germany), p. 4, Mar. 2014. | ||||
| LIRMM | S. Larguech, F. Azais, S. Bernard, V. Kerzerho, M. Comte, and M. Renovell, “A Comparative Analysis of Indirect Measurement Selection Strategies for Analog/RF Alternate Testing,” in TVHSAC’13 : Workshop on Test and Validation of High-Speed Analog Circuits, (Anaheim, United States), IEEE, Apr. 2014. | ||||
| LIRMM | Ayari, H.; Azais, F.; Bernard, Kerzerho, V.; Larguech, S.; Comte, M.; Renovell, M., “Investigations on alternate analog/RF test with model redundancy,” in Workshop on Statistical Test Methods (STEM), May 2014 Proc. 1st Workshop on Statistical Test Methods (STEM’14), Paderborn, Allemagne, Mai 2014. |
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| LIRMM / NXP-FR | S. David-Grignot, F. Azaïs, L. Latorre, F. Lefevre, “Phase Noise Measurement on IF Analog Signals Using Standard Digital ATE Resources”, Proc. IEEE International NEWCAS Conference (NEWCAS’14), Juin 2014. | ||||
| LIRMM / NXP-FR | David-Grignot, S.; Azais, F.; Latorre, L.; Lefevre, F., “Stochastic model for phase noise measurement from 1-bit signal acquisition,” in Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2014 19th International , vol., no., pp.1-6, 17-19 Sept. 2014 S. David-Grignot, F. Azaïs, L. Latorre, F. Lefevre Proc. IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW’14), p.6, Porto Alegre, Brésil, Septembre 2014 |
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| LIRMM / NXP-FR | Dieng, M.; Azais, F.; Comte, M.; Bernard, S.; Kerzerho, V.; Renovell, M.; Kervaon, T.; Pugliesi-Conti, P.H., “Study of adaptive tuning strategies for Near Field Communication (NFC) transmitter module,” in Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2014 19th International , vol., no., pp.1-6, 17-19 Sept. 2014 M. Dieng, F. Azaïs, M. Comte, S. Bernard, V. Kerzerho, M. Renovell, T. Kervaon, P.H. Pugliesi-Conti Proc. IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW’14), p.6, Porto Alegre, Brésil, Septembre 2014. |
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| LIRMM | Larguech, S.; Azais, F.; Bernard, S.; Kerzerho, V.; Comte, M.; Renovell, M., “Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing,” in Test Workshop – LATW, 2014 15th Latin American , vol., no., pp.1-6, 12-15 March 2014 S. Larguech, F. Azaïs, S. Bernard, V. Kerzerho, M. Comte, M. Renovell Proc. IEEE Latin American Test Workshop (LATW’14), p.6, Fortaleza, Brésil, Mars 2014. |
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| LIRMM / NXP-FR | David-Grignot, S.; Azais, F.; Latorre, L.; Lefevre, F., “Low-cost phase noise testing of complex RF ICs using standard digital ATE,” in Test Conference (ITC), 2014 IEEE International , vol., no., pp.1-9, 20-23 Oct. 2014 F. Azaïs, S. David-Grignot, L. Latorre, F. Lefevre Proc. IEEE International Test Conference (ITC’14), Paper.9.1, Seattle, USA, Octobre 2014. |
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| LIRMM | A. Asokan, A. Todri-Sanial, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch and A. Virazel, “Path Delay Test in the Presence of Multi-Aggressor Crosstalk, Power Supply Noise and Ground Bounce”, DDECS 2014 | ||||
| LIRMM | A. Asokan, A. Todri-Sanial, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch and A. Virazel, “A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise”, ISVLSI 2014 | ||||
| LIRMM | A. Asokan, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch and A. Virazel, “Crosstalk and Supply Noise – Aware Pattern Generation for Delay Testing”, GDR SoC-SiP 2014 | ||||
| LIRMM | A. Asokan, A. Bosio, A. Virazel, L. Dilillo, P. Girard and S. Pravossoudovitch, “Layout-Aware ATPG in the Presence of Multiple Aggressors and Supply Noise”, JNRDM 2015 | ||||
| TIMA | “Analog/RF test techniques”, Invited Tutorial, 14th European Test Symposium/Test Spring School, Paderborn, Germany, May 2014 | ||||
| TIMA | On-chip implementation of an integrator-based servo-loop for ADC static linearity test”, 23rd IEEE Asian Test Symposium, Hangzhou, China, November 2014. | ||||
| TIMA | Evaluation of digital ternary stimuli for dynamic test of Sigma-Delta ADCs”, IFIP/IEEE 22nd VLSI-SoC, Playa del Carmen, Mexico, October 2014 | ||||
| TIMA | Non-intrusive built-in test for 65nm RF LNA”, 2014 IEEE IMS3TW, Porto Alegre, Brazil, September 2014. | ||||
| UT | J. Wan, and H.G. Kerkhoff, “The influence of no fault found in analogue CMOS circuit ”, In: 2014 International Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW’14), ISBN 978-1-47996-540-3, Porto Alegre, Brazil, pp. 1-6, 17-19 Sep 2014. | ||||
| UT | J. Wan and H.G. Kerkhoff, “”New Drain Current Model for Nano-Meter MOS Transistors On-Chip Threshold Voltage Test”, in Proceedings European test Symposium (ETS), Cluj-Napoca, Romania, pp. 1-6, May 2015. | ||||
| UT | J. Wan and H.G. Kerkhoff, “Embedded Instruments for Enhancing Dependability of Analog and Mixed-Signal IPs”, in proceedings NEWCAS, Grenoble, June 2015. | ||||
| UT | J. Wan and H.G. Kerkhoff, “Reliability of SAR ADCs and Associated Embedded Instrument Detection ”, in Proc. of International Mixed-Signal Test Workshop (IMSTW), Paris, June 2015. | ||||
| UT | A. Zambrano and H.G. Kerkhoff, “Online Digital Offset Voltage Compensation Method for AMR Sensors”, in Proceeding of IEEE Instrumentation and Measurements, Pisa, Italy, May 2015. | ||||
| UT | A. Zambrano and Hans G. Kerkhoff, “Fault-Tolerant System for Catastrophic Faults in AMR Sensors”, IEEE International On-Line Test Workshop (IOLTW), Greece, July 2015. | ||||
| UT | A. Zambrano and Hans G. Kerkhoff, “Determination of the Aging Offset Voltage of AMR Sensors Based on Accelerated Degradation Test”, in Proc. International Mixed-Signal Test Workshop (IMSTW), Paris, June 2015. | ||||
| UT | A. Zambrano and Hans G. Kerkhoff, “Estimation of the Maximum Angle Error due to Offset Voltage in AMR Sensors”, submitted to IEEE Sensors, 2015. | ||||
| UT | A.M.Y. Ibrahim, and H.G. Kerkhoff, “ iJTAG integration of complex digital embedded instruments”, In: 9th International Design & Test Symposium (IDT), ISBN 978-1-4799-8200-4, Algiers, Algeria, pp. 18-23, 16-18 Dec 2014. | ||||
| UT | A. Ibrahim, H.G. Kerkhoff, “A System-Level Solution for Dependable Heterogeneous MPSoCs”, extended abstract, 45th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), in Proceedings, Rio de Janeiro, Brasil, June, 2015. | ||||
| UT | A. Ibrahim, H.G. Kerkhoff, “Error-Triggered Dependability Tests”, submitted to the 33rd IEEE International Conference on Computer Design (ICCD), Ney York USA, October, 2015. | ||||
| UT | H.G. Kerkhoff, “Dependable Mixed-Signal Integrated Systems under Aging”, invited speaker, 9th International Design & Test Symposium (IDT), Algiers, Algeria, 16-18 Dec 2014. | ||||
| IROC | Flip-Flop SEU Reduction through Minimization of the Temporal Vulnerability Factor(TVF) Adrian Evans and Enrico Costenaro (iRoC Technologies), Arkady Bramnik (Intel Corporation) – IOLTS 2015 | ||||
| IROC | A Call for Cross-Layer and Cross-Domain Reliability Analysis and Management, Dan Alexandrescu, Adrian Evans, Enrico Costenaro, Maximilien Glorieux, iRoC Technologies, – IOLTS 2015 | ||||
| FEUP | Antonio Salazar Escobar, “Mixed-signal Test and Measurement Framework for Wearable Monitoring System”, PhD Thesis, University of Porto, January 2015 | ||||
| LIRMM / NXP-FR | Azais, F.; David-Grignot, S.; Latorre, L.; Lefevre, F., “Embedded Test Instrument for On-Chip Phase Noise Evaluation of Analog/IF Signals,” in Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2015 IEEE 18th International Symposium on , vol., no., pp.237-242, 22-24 April 2015 | ||||
| LIRMM / NXP-FR | F. Azaïs, S. David-Grignot, L. Latorre, F. Lefevre, “A digital technique for the evaluation of SSB phase noise of analog/RF signals”, Proc. IEEE Latin American Test Symposium (LATS’15), Mars 2015. | ||||
| LIRMM / NXP-FR | David-Grignot, S.; Azais, F.; Latorre, L.; Lefevre, F., “Digital on-chip measurement circuit for built-in phase noise testing,” in Mixed-Signal Testing Workshop (IMSTW), 2015 20th International , vol., no., pp.1-6, 24-26 June 2015 | ||||
| LIRMM / NXP-FR | David-Grignot, S.; Azais, F.; Latorre, L.; Lefevre, F., “A new technique for low-cost phase noise production testing from 1-bit signal acquisition,” in Test Symposium (ETS), 2015 20th IEEE European , vol., no., pp.1-6, 25-29 May 2015 | ||||
| LIRMM | Larguech, S.; Azais, F.; Bernard, S.; Comte, M.; Kerzerho, V.; Renovell, M., “A generic methodology for building efficient prediction models in the context of alternate testing,” in Mixed-Signal Testing Workshop (IMSTW), 2015 20th International , vol., no., pp.1-6, 24-26 June 2015 | ||||
| LIRMM | Larguech, S.; Azais, F.; Bernard, S.; Comte, M.; Kerzerho, V.; Renovell, M., “A framework for efficient implementation of analog/RF alternate test with model redundancy,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), vol., no., pp.1-6, 8-10 July 2015 | ||||
| LIRMM | Larguech, S.; Azais, F.; Bernard, S.; Comte, M.; Kerzerho, V.; Renovell, M., “Efficiency evaluation of analog/RF alternate test: comparative study of indirect measurement selection strategies”, Accepted at Microelectronics Journal (MEJO) | ||||
| LIRMM / NXP-FR | Azais, F.; David-Grignot, S.; Latorre, L.; Lefevre, F., “Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits,” accepted at Journal of Circuits, Systems, and Computers (JCSS) | ||||
| LIRMM / NXP-FR | V. Kerzerho, F. Azaïs, M. Dieng, M. Comte, S. Bernard, M. Renovell, P.-H. Pugliesi-Conti, and T. Kervaon, “Self-Adaptive NFC Systems,” in IOLTS’14 : 20th International On-Line Testing Symposium, Special Session 4 – Solutions for the self-adaptation of communicating systems in operation, (Platja d’Aro, Spain), IEEE, July 2014. | ||||
| LIRMM | A. Asokan, A. Bosio, A. Virazel, L. Dilillo, P. Girard et S. Pravossoudovitch, “An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern”, IEEE ISVLSI 2015 | ||||
| NXP-NL | Nanoelectronic Forum: European Library based Flow of Embedded Silicon Test Instruments, 26-27 November 2014, Cannes, France | ||||
| NXP-NL | Nanoelectronic Forum: Demo on Test Access Interface for Temperature Sensor, 26-27 November 2014, Cannes, France | ||||
| ST | Nanoelectronic Forum: Demo on Jitter measurement using ETI, 26-27 November 2014, Cannes, France | ||||
| NXP-NL | ETS15, RAFE Workshop: Keynote speaker: Challenges of Testing in Europe | ||||
| TIMA/CEA | A. Dimakos, H.-G. Stratigopoulos, A. Siligaris, S. Mir and E. de Foucauld. “Parametric built-in test for 65 nm RF LNA”, JETTA, August 2015 | ||||
| TIMA/ST | H.-G. Strangulations, M. Barragán, S. Mir, H. Le Gall, N. Bhargava and A. Bal. “Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times”, IEEE ITC, October 2015. | ||||
| TIMA | A. Dimakos, M. Andraud, L. Abdallah, H.-G. Strangulations, E. Simeu and S. Mir. “Test and calibration of RF circuits using built-in non-intrusive sensors”, IEEE International Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, July 2015. | ||||
| TIMA | G. Renaud, M. Barragán and S. Mir. “Design of an on-chip stepwise ramp generator for ADC static BIST applications”, IEEE International Mixed-Signal Testing Workshop, Paris, France, June 2015 | ||||