The ELESIS project is focussed on improving the industrial test infrastructure for Integrated Circuits, leading to safe, reliable, high quality and low cost semiconductors products in Europe. The project is relevant to the Design Technologies domain and is addressing the Grand Challenges managing complexity, managing diversity and design for reliability and yield.
Measurable advantages [ELESIS Key Performance Indicators]:
- Test cost reduction for non-logic tests of 50% for a composed reference design consisting of analogue, RF, digital and memory blocks. Test cost of the pure digital and memory part are excluded in the calculation.
- Average test development time reduction of 40% for a test flow of the reference design.
- Reduction in diagnosis time of non-logic blocks of 50%.
- Average yield-loss reduction by adjustment of 50%.
ELESIS is a very ambitious project which plans to cover the mentioned targets (Safety, reliability, high quality and low cost) for mixed signal circuits in addition to digital, with special focus on Analog, RF and Sensors. The ELESIS project will also target a European Standard Interface to reduce test complexity and to manage access to the internal IP blocks from the top level IC. We will address the most important aspects of semiconductor testing within a framework of so-called “embedded test instruments” controlled through a common interface that is needed to ensure the best solutions to reach our challenging targets. The proposed standard interface will have a large economic impact by the creation of an Open Source Platform, which could be used by IP, IDM and Fabless companies in Europe and even worldwide.
In the coming years European Semiconductor companies will bring many new applications to to the market to improve the way of living in Europe. Examples are linked to road safety, personal health care, secured wireless communications, lighting and consumer electronics. These applications concern very complex semiconductor systems with highly integrated technologies where digital, memories and analogue are funnelled in one piece of silicon. In these kind of applications, reliability and trustability is a key factor which cannot be guaranteed without extensive test solutions. This may lead to expensive and unreliable test solutions when necessary preventive efforts are omitted. The ELESIS project provides cooperation between leading semiconductors companies in Europe, small and medium enterprises that are dedicated to system test and tooling and well-recognized European Institutes and Universities. This consortium will certainly be able to integrate and industrialise the above-mentioned framework.
The production testing of Integrated Circuits (ICs) is, currently, carried-out resorting to large and expensive Automated Test Equipment (ATE). A disadvantage of this approach is that while the production cost of a transistor decreases with each new technology node, the cost of testing remains flat or increases, particularly for ICs with analogue, RF or sensors components (concerning ~80% of IC test costs). If test features are built into the chip, making therefore part of the silicon, they would ensure that the benefits of silicon scaling to new technology nodes translate to benefits in testing cost. The concept of Built-In Self-Test (BIST) is a well-known solution for digital logic and memories but it is still in its infancy as far as analogue, RF and sensors are concerned. Although solutions do exist for analogue, RF and sensor blocks they are typically ad-hoc and point solutions and are only applicable to a specific block. While it does reduce recurring test cost, it will increase design and test development costs. Moreover, it increases the time to market and risks since a new test solution has to be made for each design. To really benefit from this self-test concept, generic BIST solutions which rely on standard embeddable testing resources are required. Furthermore, to ensure fast test integration and interoperability these generic BIST solutions require a common access and control interface.
Structural based BIT (Built-In-Test) solutions greatly improve test efficiency and cost, but test coverage (in terms of defect detection and/or parameters’ observation) could be not enough for a given component. In order to increment test coverage, both BIST and functional test solutions are required. Hereafter, a hardware test solution, driven by a BIT approach and improved with functional test capabilities, is called a test instrument.
Another advantage of the BIT approach is that ICs can be tested in parallel which would further reduce test cost. BIT also enables checking ICs during their lifetime and either provides an early warning or adjusts the performance and thereby prevents a malfunction. Finally, embedded test instruments can also provide crucial information for facilitating failure diagnosis at any moment in the device life, eventually helping for device repair.
The ELESIS project addresses these challenges for test and reliability by promoting the development of a framework of embedded test instruments which are controlled through a common interface. Key characteristics of the embedded test solutions delivered by ELESIS are:
- A standardized common control interface, defined within the project
- Efficient and low cost test solutions for analog and digital circuits which can be used in many different applications and come close to a generic solution.
- Development of new methodologies for yield and reliability analysis.
- Optimized capabilities regarding silicon area versus accuracy.
- Transparency with respect to the device normal function.
- Easily testable with low probability of failure due to the reduced area.
- Methods for integration and industrialization of the proposed solutions.