FR20120054611
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Patent Information |
Title |
DISPOSITIF DE TEST ET DE MONITORING DE CIRCUITS NUMERIQUES |
Application Number |
FR20120054611 |
Publication Number |
2990764 (A1) |
Application Date |
May 21, 2012 |
Publication Date |
November 22, 2013 |
Inventor |
GHERMAN VALENTIN FR |
Assignee |
COMMISSARIAT ENERGIE ATOMIQUE FR |
IPC |
G01R 31/3187 |
Dispositif de test et de surveillance ou monitoring de circuits numériques destinés à être inséré dans des chaînes de scan, et son procédé, le dispositif comprenant au moins un élément d’échantillonnage primaire d’un signal D et au moins un élément d’échantillonnage secondaire du signal D , ledit élément d’échantillonnage secondaire étant disposé en aval d’un module de contrôle logique ou logique scan, un signal d’activation du mode d’observation et contrôle ou scan enable agit au niveau du premier et du second élément d’échantillonnage afin que le dispositif fonctionne dans un mode scan ou dans un mode fonctionnel, un signal d’horloge transmis audit élément d’échantillonnage primaire et audit élément d’échantillonnage secondaire, un module fournissant un signal de remise à zéro ou reset dudit élément d’échantillonnage primaire.
20131000012338 0198
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Patent Information |
Title |
Mixed-Signal Test and Measurement Framework for Monitoring Systems |
Application Number |
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Publication Number |
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Application Date |
H1 2013 |
Publication Date |
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Inventor |
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Assignee |
FEUP |
EP20120354035
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Patent Information |
Title |
Robust circuit protected against transient perturbations and timing faults |
Application Number |
EP20120354035 |
Publication Number |
EP2675067 A1 |
Application Date |
June 12, 2012 |
Publication Date |
December 18, 2013 |
Inventor |
Michel Nicolaidis, Dan Alexandrescu |
Assignee |
iRoC Technologies |
A circuit comprises a combinatory logic circuit having one input and one output. First and second sampling elements are connected to the output and sample this output respectively at the activation of a first and second latching events determined by an event of first and second clock signals (CK). The event of second clock signal (CK) is delayed with respect to the event of a first clock by a delay which is shorter than the clock period. An analysis circuit analyzes the outputs of the first and the second sampling elements and provides an error detection signal. The analysis circuit sets the error detection signal (E) at the pre-determined value if the outputs of the first and second sampling elements are different. The circuit is used in a first operating mode in which the event of a second clock (CK) determining the second latching event is delayed with respect to the event of first clock (CK) determining the first latching event by a delay which is larger than a largest delay of the circuit.
lirmm-00985404
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Patent Information |
Title |
Method And Apparatus For Measuring Phase Noise |
Application Number |
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Publication Number |
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Application Date |
October 17, 2013 |
Publication Date |
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Inventor |
Florence Azais (1), Laurent Latorre (1), Stéphane David-Grignot (1, 2), François Lefevre (2) |
Assignee |
(1) LIRMM, (2) NXP |
FR 13 60127
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Patent Information |
Title |
Signal analysis apparatus for testing and monitoring transfer functions |
Application Number |
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Publication Number |
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Application Date |
H2 2013 |
Publication Date |
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Inventor |
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Assignee |
ST |
EP13191370.9
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Patent Information |
Title |
Functional unit for a processor |
Application Number |
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Publication Number |
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Application Date |
H1 2014 |
Publication Date |
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Inventor |
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Assignee |
UT |
107 537
|
Patent Information |
Title |
Mixed signal bus module for multiple circuit resources management |
Application Number |
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Publication Number |
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Application Date |
March 3, 2014 |
Publication Date |
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Inventor |
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Assignee |
FEUP |