The ELESIS project aims to increase European Integrated Circuits (IC) quality and competitiveness by developing generic embeddable test instruments and interfaces which will improve their testability and reliability, controlled through a common interface hence, ensuring lower overall cost of goods, shorter time to market and higher quality products.
These auxiliary test features will also promote systems’ maintainability and reliability when in operating in the field, with the additional advantage of these may being carried-out in-situ by means of built-in self test and diagnosis operations, as well as being activated with different external equipment developed following widespread standards.
Key guidelines of the embedded test solutions are:
- Adopt a common control interface, defined within the project.
- Provide solutions which can be used in many different applications close to a generic solution.
- Present optimized capabilities regarding silicon area versus accuracy
- Are transparent with respect to the device normal function
- Are easily testable with low probability of failure due to the reduced area
The following table presents the list of IPs proposed in the framework of the project. Clicking on a IP number will open the relevant page or datasheet. Columns can be sorted by clicking on the respective headers.
| IP | Partner(s) | Name & Type | Overview & Objectives | Dissemination & Format |
|---|---|---|---|---|
| 01 | TEMENTO | SPS DDR3 Digital IP for Board and FPGA |
The IP Defect DDR3 SDRAM (SPS DEF DDR3) is now available through Temento Systems IPs product family. This test IP is executed by any FPGA/CPLD that checks all industry-standard DDR3 SDRAM memories in the aim to detect defects such as open, stuck at 0/1 and short-circuit on data, (bank address and address busses) | Open to Licensing Synthesized netlist |
| 02 | ST, TIMA, TEMENTO | Analog Front-end for jitter BIST Mixed IP for ASIC, Board & FPGA |
This test instrument is aimed to evaluate clock signals generated from PLL circuits by measuring their jitter. The validation of this IP has been performed on an FPGA (Field-Programmable Gate Array) platform. This platform provides flexibility for modifying the Flip-Flop chain length at the input of the jitter BIST to understand limitations due to meta-stability phenomena and power-supply noise. For measuring the impact of power supply noise, external circuitry is added to see the impact on the jitter measurement. | Open to Licensing Guidelines to get adapted measurement |
| 03 | ST, TEMENTO | Jitter map BIST Mixed IP for ASIC, Board and FPGA |
Elaborate a jitter map on SoC | Open to Licensing Synthesized netlist |
| 04 | ST, TIMA | ADC Pipeline BIST Mixed IP for ASIC |
This test instrument is aimed at the on-chip characterization of the dynamic performance of discrete-time Sigma-Delta ADCs. The proposed BIST IP includes an innovative ternary test stimulus generator that allows an accurate estimation of the SNDR of the converter at input amplitudes very close to the FS range. Signal analysis is performed using a simplified version of the sine-wave fitting algorithm, and the functionality of the complete IP can be managed through a standard SPI controller. | Open to Licensing Netlist (custom and synthesized parts) |
| 05 | ST, TIMA | ADC Sigma-Delta BIST Mixed IP for ASIC |
Dynamic BIST for Sigma-Delta ADCs This test instrument is aimed at the on-chip characterization of the dynamic performance of discrete-time Sigma-Delta ADCs. The proposed BIST IP includes an innovative ternary test stimulus generator that allows an accurate estimation of the SNDR of the converter at input amplitudes very close to the FS range. Signal analysis is performed using a simplified version of the sine-wave fitting algorithm, and the functionality of the complete IP can be managed through a standard SPI controller. |
Open to Licensing Synthesized netlist |
| 06 | ST, TIMA | Static servo-loop test of pipeline ADCs Mixed IP for ASIC |
This generic test instrument is aimed at the on-chip characterization of the static performance of ADCs. The proposed test instrument IP is a discrete-time ramp stimulus generator that allows triggering the comparator levels of the converter with an integration step of 1/10000 of the input DC level Vin. The functionality of the IP is controlled through the clock and reset digital inputs and requires two analog DC references. | Open to Licensing Custom netlist |
| 07 | NXP-FR, LIRMM | Phase Noise Embedded Test Instrument Mixed IP for ASIC |
Low cost phase noise test The IP PN-ETI2 is a low area module for on-chip evaluation of complex phase noise frequency-domain characteristics on analog/IF signals. It relies on oversampled 1-bit conversion of the analog signal and a dedicated on-the-fly processing of the resulting binary vector. It delivers a digital signature related to the phase noise level present in the analog signal at a given frequency offset. The module is parametrizable to different values of the measurement frequency offset allowing evaluation of phase noise spectrum. |
Open to Licensing Synthesized netlist |
| 08 | TIMA, CEA | Embedded non intrusive sensors Analog & RF IP for ASIC |
Low-cost test of RF front-end | Open to Licensing Custom netlist |
| 09 | IROC | 45nm SER Database Digital IP for ASIC |
The 45nm SER Database present Neutron and Alpha Particles Soft Error Rate data for the Nangate 45nm Open Cell Library obtained from a simulation-based analysis. The Nangate 45nm Open Cell Library is an open-source, standard-cell library provided for the purposes of testing and exploring EDA flow. The SER Database is useful to researchers and engineers looking for solutions and data for design-flow oriented SER reliability analysis of complex circuits. The presented data can be used in manual or tool-assisted computations. |
Open Source/Public Textual reports,SQL database, CSV, XLS files |
| 10 | NXP-FR, LIRMM | Phase Noise Embedded Test Instrument Mixed IP for ASIC |
Low cost phase noise test The IP PN-ETI1 is an ultra-low area module for on-chip evaluation of 1/f2 phase noise on analog/IF signals. It relies on oversampled 1-bit conversion of the analog signal and a dedicated on-the-fly processing of the resulting binary vector. It delivers a digital signature related to the phase noise level present in the analog signal. |
Open to Licensing Synthesized netlist |
| 11 | FEUP | Control state machine for I2C based test bus Digital IP for Board & FPGA |
The SCPS framework provides a flexible inter-communication means, among compliant test instruments, permitting ease of management of inter-dependent and intra-modular task sets, resorting to the I2C bus standard. Interlinking of analog, mixed-signal and sensor test instrument is the main target; however, the IP also provides advantages for standalone cores through syntax simplification. The SCPS Controller implements the control state machine required to translate the SCPS instructions into I2C bus operations, as well as manage the associated registers and mechanism. | Open to Licensing Verilog |
| 12 | Infineon-AT | ADC BIST Mixed IP for ASIC |
BIST for static and dynamic ADC parameters | Open to Licensing Synthesized netlist |
| 13 | NXP-NL | Manchester Test Interface Digital IP for ASIC |
The Manchester adaptor interface requires one pin on the chip package for data, clock and test mode settings. In addition a second pin on the chip package is required to transfer data off-chip to a tester system. The interface can be multiplexed with other functional pins. The one wire test interface incorporates decoding hardware to interface with an embedded on-chip JTAG TAP controller. This ensures compatibility without the disadvantages of the 4 or 5 pin requirement for JTAG. The one wire protocol for input data is based on a Manchester coding/decoding. The clock and data signals are combined into an encoded signal. A logic one is represented by a zero to one transition, and a logic zero is represented by a one to zero | ELESIS Partners Synthesized netlist |
| 14 | NXP-NL | TAPSCAN Test Interface Digital IP for ASIC |
The TapScan adaptor interface is an on-chip structure that allows production test of digital logic, memories and analog mixed signal to use JTAG protocols and SCAN protocols repeatedly in any order both sharing same 4 chip pins. Additional control to switch configurations is no longer required. The JTAG protocol comes with a state machine that traverses states based on the TMS data input pin and clock TCK. The TDI data input pin is assigned a function in a subset of the states. During the Run Test Idle state in which scan test typically is executed the TDI pin is not assigned a function. This Adaptor implements a mapping of pins that allows a standard SCAN protocol to coexist with the JTAG protocol in RTI state when a dedicated JTAG instruction is loaded for this purpose. |
ELESIS Partners RTL files |
| 15 | TEMENTO | SPS SDRAM QDRII+ Digital IP for Board & FPGA |
The IP Defect QDRII+ (SPS DEF QDR2+) is now available through Temento Systems IPs product family. This Embedded Micro Tester (EMT) can be executed by any FPGA/CPLD that checks all industry-standard QDRII+ SRAM memories in the aim to detect defects such as open, stuck at 0/1 and short-circuit on both data and address busses | Open to Licensing Synthesized netlist |
| 16 | TEMENTO | SPS LVDS Digital IP for Board & FPGA |
The test IP GoNoGo Extended LVDS (SPS GNGEXT LVDS) is now available through Temento Systems IPs product family. This test IP is executed by any FPGA/CPLD that checks the reliability of a LVDS communication link by sending random patterns. | Open to Licensing Synthesized netlist |
| 17 | University of Twente | Basic Dependability manager – Generic Test Respons Evaluator Digital IP for ASIC |
The generic Test Response Evaluator (TRE) instrument is mainly used in BIST-like systems for evaluating IP test responses against the fault-free ones. This is done by time-compacting the responses to a single small sized signature. The proposed evaluator instrument has an iJTAG reconfiguration capability so the IP user would configure through iJTAG different parameters according to the required specifications. | Open Source/Public Synthesized netlist |
| 19 | University of Twente, NXP-NL | Output voltages of AMR sensors Mixed IP for ASIC |
Measure the output voltages of an Anisotropic Magnetoresistance sensor (AMR sensor) | Open to Licensing Custom netlist |
| 20 | University of Twente | SAR ADC ageing instrument Mixed IP for ASIC |
The NBTI ageing influence for the overall performance of the ADC can be timing errors and offset errors. The timing error is mainly due to the increased delay from the self-timing asynchronous SAR logic. The offset errors is due to the ageing induced offset in the comparator. To prevent reliability induced time error and offset error. An embedded instrument is proposed to address both the SAR ADC timing error and offset error. | Open Source/Public Custom netlist |
| 21 | University of Twente | MOSFET threshold voltage instrument Mixed IP for ASIC |
The proposed IP can measure the transistor threshold voltage shift which is caused by ageing (reliability effects). The IP use a new MOS model for the Nano-meter MOS transistor drain current which is continuously valid from the sub-threshold regime till the strong-inversion regime. The use of new model reduces both complexity and high-accuracy requirements of threshold-voltage measurements and make the IP suitable for extracting the MOS threshold-voltage via on-chip general-purpose ADCs and DACs. The IP can cancel the temperature influence on the threshold voltage and make sure that the shift in threshold voltage is come from ageing. | Open Source/Public Custom netlist |
| 22 | University of Twente | OpAmp offset and again instrument Mixed IP for ASIC |
Reliability effect in CMOS, like NBTI, can influence the offset of OpAmps. So an embedded instrument IP for analog OpAmp tests is proposed in this document. It can provide the exact gain and offset values of OpAmps instead of only pass\slash fail result. What's more, it is an non-invasive monitor and can work online without isolating the DUT OpAmp from its surrounding feedback networks. Nor does it require accurate test stimulations. In addition, the embedded instrument can remove its own offsets without additional complex self-calibration circuits. All self-calibrations are completed in the digital domain after each measurement in real time. Therefore it is also suitable for aging-sensitive applications, in which the monitor may suffer from aging mechanisms and has additional offset drifts as well. | Open Source/Public Custom netlist |
IP Tools
| IP Tool | Partner(s) | Name & Type | Overview & Objectives | Dissemination & Format |
|---|---|---|---|---|
| T01 | D4T | DMS – Dependability Model Simulator EDA tool for ASIC, Board and FPGA |
With Dependability Model Simulator, the customer can validate the capability of multiple ELESIS IP monitors on his target DUT. DMS performs instrument modelling and processing of the ELESIS IP, and allows for quick “what-if” scenario testing to find the best matching IP for the target DUT. The instrument properties are embedded in the DMS tool library. The user does not need to worry about the model functionality and parameter set. The tool operates independent of the EDA environment. | Open to Licensing EDA Tool |
| T02 | Infineon Technologies Austria AG | Pattern Development for Mixed-Signal SoC | This IP Tool supports the generation of test pattern for Mixed-Signal IP, like ADC, PLL, PMS, etc. It provides a high-level pattern definition language for standard test interfaces (JTAG, SPI, I2C). In addition, analog stimulus and response/capture data can be defined in the source file. The mixed-signal test pattern can be verified by using Test-Simulation, and can be compiled into various ATE formats (Teradyne J750, FLEX; Advantest V93k) | ELESIS Partners EDA Tool |
| T03 | Infineon Technologies Austria AG | Test-Simulation for Mixed-Signal SoC | This IP Tool supports the pre-silicon simulation and verification of mixed-signal test patterns | ELESIS Partners EDA Tool |
| T04 | JTAG Technologies | IEEE 1687 PDL player | The IEEE1687 PDL executer is a software tool that is capable of playing IEEE1687 PDL (Procedural Description Language) files. The tool is an addon to the JFT/Script application types in the JTAG Technologies’ Provision Test development and deployment platform. The PDL player uses a description of the IEEE1149.1 boundary-scan chain architecture which is build from the Boundary-scan Description Language (BSDL) files of the boundary-scan components. A device with an IEEE1687 network also has an Instrument Connectivity Language (ICL) file that describes the IEEE1687 network inside the device. This file is linked to a boundary-scan device in the boundary-scan chain. The information in the PDL file is then combined with the data streams that are needed to control the network in such a way that the instrument can be accessed. | Open to Licensing EDA Tool |
| T05 | LIRMM | IT-GenFrame | IT-GenFrame is a Generic Framework for the evaluation and optimization of Indirect Test for analog/RF circuits. It constitutes an essential element to guide the design and test engineers regarding practical aspects of alternate test implementation, including the choice of the embedded test instruments and the setting of test parameters. It also gives an evaluation of the test efficiency that can be expected under different test scenarios. | Open to Licensing EDA Tool |
| T06 | LIRMM, NXP | Phase Noise Software Test Instrument: PN-STI1 | PN-STI1 is a software test instrument that permits 1/f^2 phase noise testing of analog/IF signals from oversampled 1-bit capture realized by a standard digital ATE channel. It therefore offer a low-cost test solution since it permits to get rid of the analog/RF test resources required for the conventional phase noise measurement. It also offers the possibility to implement multi-site testing. | Open to Licensing EDA Tool |
| T07 | LIRMM, NXP | Phase Noise Software Test Instrument: PN-STI2 | PN-STI2 is a software test instrument that permits evaluation of complex phase noise frequency-domain characteristics of analog/IF signals from oversampled 1-bit capture realized by a standard digital ATE channel. It therefore offer a low-cost test solution since it permits to get rid of the analog/RF test resources required for the conventional phase noise measurement. It also offers the possibility to implement multi-site testing. | Open to Licensing EDA Tool |
| T08 | LIRMM | SIM-ISSS | Sim-ISSS is a tool for the selection of pertinent indirect measurements in the context of indirect test for analog/RF circuits. These indirect measurements can be gathered either from external tests or from embedded test instruments. This tool therefore helps in defining which are the more appropriate embedded test instruments to be used for efficient implementation of the alternate test strategy. It also gives an evaluation of the test efficiency that can be expected using the selected subset of indirect measurements. | Open to Licensing EDA Tool |
| T09 | NXP-NL | DOTSS | Defect Oriented Test Simulation System, DOTSS, is a framework that supports designers, test engineers and failure analysis engineers to perform defect analyses of AMS designs. DOTSS aims test set optimization, defect coverage improvement and accurate electrical diagnosis. | Open to Licensing EDA Tool |